Video
Onsite
No H1
Job Summary
We are looking for a skilled Physical Design Engineer with extensive experience in MCU/MPU SoC design. You will play a crucial role in the physical design activities, including floorplanning, placement, routing, and verification. The ideal candidate will have a strong background in using industry-standard tools such as Synopsys Fusion Compiler and Cadence Innovus.
Key Responsibilities
- Physical Design: Lead physical design tasks for MCU/MPU SoCs, including floorplanning, placement, clock tree synthesis (CTS), routing, and DRC cleanup.
- Implementation: Execute place and route activities using Synopsys and Cadence tools, ensuring designs meet performance, power, and area requirements.
- Chip-Level Design: Perform chip-level synthesis, formal verification (LEC), and low-power intent signoff (CLP).
- Optimization: Optimize designs for performance, power, and area, addressing any issues related to physical verification, IR drop, and power delivery network (PDN).
- Cross-Functional Collaboration: Work with Static Timing Analysis (STA) teams to assist in timing closure and ensure successful integration of designs.
- Multi-Site Coordination: Manage and execute tasks across multiple sites and teams to achieve project goals.
Key Challenges
- Demonstrate in-depth knowledge of synthesis and place-and-route for diverse design types.
- Efficiently coordinate with multi-site teams to ensure seamless execution of physical design tasks.
Required Skills
- Experience: 3-10 years of experience in physical design with a strong background in MCU/MPU SoC design.
- Tools: Proficiency in using Synopsys Fusion Compiler and Cadence Innovus.
- Design Skills: Expertise in floorplanning, placement, clock tree synthesis (CTS), routing, DRC cleanup, and extraction.
- Chip-Level Expertise: Proven experience in chip-level synthesis, formal verification (LEC), and low-power intent signoff (CLP).
- Cross-Functional Collaboration: Ability to work with STA teams for timing closure and manage multi-site coordination.
- Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.
Preferred Qualifications
- Experience with physical verification, IR drop analysis, and power delivery network (PDN) assessment.
- Familiarity with scripting and automation to enhance design efficiency.